This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Integrated circuits can be designed as memory. In Read-Only Memory (ROM) designs, low leakage and high density are important considerations. Low leakage can be achieved by selectively pulling a voltage supply line (VSB line) to 0 based on a selected column. However, density can be limited by a number of maximum bitcells that can be connected to a single bitline, which can decide a number of rows per bitcells or a number of rows per bank. The rows per bitline can be governed by a leakage of a bitcell, and the more leaky the bitcell, the lesser rows per bitline. Therefore, additional memory banks may be needed. In some cases, local input/output (IO) needed for each bank can increase a memory area by up to approximately 30%.
FIG. 1 shows a conventional bank type architecture 100 for ROM, where the entire memory can be divided into a number of banks. As shown, each bank can have top and bottom arrays sharing a same local IO (LIO) and sensing circuit. During operation, when any bitcell is accessed, the VSB line corresponding to a selected column is pulled low. Based on programming, the bitline (BL) either discharges or remains at VDD. The maximum number of rows that can be accommodated in each bank, (e.g., upper and lower) can be governed by leakage contribution coming from all unselected bitcells. Thus, banks may have to be duplicated, thus resulting in an increase in area to accommodate the logic associated with the local IO, which may further penalize the area.